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cy25568 spread spectrum clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07111 rev. *d revised july 18, 2011 features 4 to 32 mhz input frequency range 4 to 128 mhz output frequency range accepts clock, crysta l and resonator inputs 1x, 2x and 4x frequency multiplication non-modulated reference frequency output center and down spread modulation low power dissipation ? 3.3 v = 52 mw-typ at 6 mhz ? 3.3 v = 60 mw-typ at 12 mhz ? 3.3 v = 72 mw-typ at 24 mhz power-down mode low cycle-to cycle jitter ? 8 mhz = 195 ps-typ ? 16 mhz = 175 ps-typ ? 32 mhz = 100 ps-typ available in 16-pin (150-mil.) soic package applications printers and mfps lcd panels and monitors digital copiers pdas automotive cd-rom, vcd and dvd networking, lan/wan scanners modems embedded digital systems benefits peak emi reduction by 8 to 16db fast time to market cost reduction reference divider pd and cp lf vco vco counter divider and mux input decoder logic 1 13 16 3 300k modulation control vdd vss xin xout frsel 11 8pf 8pf 9 8 6 7 5 1 5 1 4 1 0 4 s1 so d1 do pd# 12 2 refout ssclk1 ssclk2 ssclk3 vdd vss logic block diagram
cy25568 document number: 38-07111 rev. *d page 2 of 14 contents pinouts .............................................................................. 2 pin definitions .................................................................. 2 general description ......................................................... 2 absolute maximum ratings ............................................ 3 dc electrical characteristics .......................................... 3 timing electrical characteristics .................................... 3 input frequency range and selection ........................... 4 output clocks ........... .............. .............. .............. ......... 4 refout ...................................................................... 4 ssclk1, 2 and 3 ......................................................... 4 spread% selection ........................................................... 5 3-level digital inputs ........... .............. .............. ............ 5 power down (pd#) ................. ..................................... 6 modulation rate .... ...................................................... 6 characteristic curves ...................................................... 7 sscg profiles ............................................................. 8 application schematic ..................................................... 9 ordering code definitions ..... ...................................... 9 package diagram ............................................................ 10 acronyms ........................................................................ 11 document conventions ................................................. 11 units of measure ....................................................... 11 document history page ................................................. 12 sales, solutions, and legal information ...................... 13 worldwide sales and design s upport ......... .............. 13 products .................................................................... 13 psoc solutions ......................................................... 13
cy25568 document number: 38-07111 rev. *d page 3 of 14 pinouts figure 1. cy25568 - 16 pin soic general description the cypress cy25568 is a spread spectrum clock generator (sscg) ic used for the purpose of reducing electro magnetic interference (emi) found in today's high-speed digital electronic systems. the cy25568 uses a cypress proprietary phase-locked loop (pll) and spread spectrum clock (ssc) technology to synthesize and modulate the frequency of the digital clock. by frequency modulating the clock, the measured emi at the fundamental and harmonic frequencies is greatly reduced. this reduction in radiated energy can significantly reduce the cost of complying with regulatory agency requirements and improve time to market without degrading system performance. the cy25568 input frequency range is 4 to 32 mhz and accepts clock, crystal, and ceramic reso nator inputs. the output clocks can be programmed to produce 1x, 2x, and 4x multiplication of the input frequency with spread spectrum. a separate non-modulated reference clock is also provided. the use of 2x or 4x frequency multiplication eliminates the need for higher order crystals and allows the user to generate up to 128 mhz spread spectrum clock (ssc) by using only first order crystals. this reduces the cost while improving the system clock accuracy, performance and complexity center spread or down spread frequency modulation can be selected by the user based on 4 discrete values of spread% for each spread mode with the option of a non-spread mode for system test and verification purposes. the cy25568 is available in a 16 pin soic (150-mil.) package with a commercial operating te mperature range of 0 to 70 ? c. contact cypress for availability of ?25 to +85 ? c industrial temperature range operation. refer to cy25811/12/14 products for 8-pin soic package versions of the cy25568. pin definitions pin function description 1 xin/clk clock, crystal or ceramic resonator input pin 2v ss power supply ground. 3v ss power supply ground. 4 s1 digital spread% control pin 3- level input (h-m-l). default= m. 5 s0 digital spread% control pin 3- level input (h-m-l). default= m. 6 ssclk1 output clock. refer to table 2 on page 5 for frequency programmability. 7 refout reference clock output. the same frequency as xin/clk input. 8 ssclk3 output clock. refer to table 2 on page 5 for frequency programmability. 9 ssclk2 output clock. refer to table 2 on page 5 for frequency programmability. 10 pd# power-down control internally pulled to v dd , default= high. 11 frsel input frequency range selection digital control input 3-level input (h-m-l). default= m. 12 v dd positive power supply. 13 v dd positive power supply. 14 d0 3-level (h-m-l) digital output clock scaling control. refer to table 2 on page 5 . default= m. 15 d1 3-level (h-m-l) digital output clock scaling control. refer to table 2 on page 5 . default= m. 16 xout crystal or ceramic resonator output pin 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 xout d1 d0 vdd vdd frsel pd# ssclk2 xin/clkin vss vss s1 s0 ssclk1 refout ssck3 cy25568
cy25568 document number: 38-07111 rev. *d page 4 of 14 absolute maximum ratings [1] exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. supply voltage (v dd ): ................................................. +5.5 v input voltage relative to v dd : ............................... v dd +0.3 v input voltage relative to vss : ............................... v ss ?0.3 v operating temperature: ........................................ 0 to 70 ?? c storage temperature: .................................. ?65 to +150 ?? c note : operation at any absolute maximum rating is not implied. dc electrical characteristics test conditions: v dd =3.3 v, t=25, unless otherwise noted symbol parameter min typ. max unit conditions vdd power supply range 2.90 3.3 3.60 v vinh input high voltage 0.85 v dd v dd v dd v s0,s1,d0,d1 and frsel inputs vinm input middle voltage 0.40v dd 0.50v dd 0.60v dd v s0,s1,d0,d1 and frsel inputs vinl input low voltage 0.0 0.0 0.15v dd v s0,s1,d0,d1 and frsel inputs vinh1 input high voltage 2.0 - - v pd# input only vinl1 input low voltage - - 0.8 v pd# input only voh1 output high voltage 2.4 - - v ioh = 4 ma, all output clocks voh2 output high voltage 2.0 - - v ioh = 6 ma, all output clocks vol1 output low voltage - - 0.4 v iol = 4 ma, all output clocks vol2 output low voltage - - 1.2 v iol = 10 ma, all output clocks cin1 input capacitance 6.0 7.5 9.0 pf xin (pin 1) and xout (pin 16) cin2 input capacitance 3.5 4.5 6.0 pf all digital inputs idd1 power supply current - 13.0 16.0 ma fin=4 mhz, no load (refer to figure 4 on page 8 ) idd2 power supply current - 28.0 32.0 ma fin=32 mhz, no load (refer to figure 4 on page 8 ) idd3 power supply current - 300 400 a pd#=gnd timing electrical characteristics test conditions: v dd =3.3 v, t=25 c, cl=15pf. rise/fall time at 0.4 and 2.4 v, duty cycle at 1.5 v symbol parameter min typ. max unit conditions iclkfr input frequency range 4 32 mhz clock, crystal or ceramic resonator input trise1 clock rise time 2.4 3.2 4.0 ns ssclk1,2, and 3, all cases when 1x or 2x scaling selected, when 4x if frsel=1 or 0 tfall1 clock fall time 2.4 3.2 4.0 ns ssclk1,2, and 3, all cases when 1x or 2x scaling selected, when 4x if frsel=1 or 0 trise2 clock rise time 1.2 1.6 2.0 ns ssclk2, and 3, only when 4x scaling is selected and frsel=m tfall2 clock fall time 1.2 1.6 2.0 ns ssclk2, and 3, only when 4x scaling is selected and frsel=m trise3 clock rise time 2.4 3.2 4.0 ns refout only tfall3 clock fall time 2.4 3.2 4.0 ns refout only cdcin input clock duty cycl e 20 50 80 % xin/clk (pin 1) cdcout output clock duty cycle 45 50 55 % ssclk1,2 and 3 ccj1 cycle-to-cycle jitter - 195 260 ps fin=8 mhz (refer to figure 4 on page 8 ) ccj2 cycle-to-cycle jitter - 170 225 ps fin=16 mhz (refer to figure 4 on page 8 ) notes 1. single power supply: the voltage on any input or io pin cannot exceed the power pin during power-up.
cy25568 document number: 38-07111 rev. *d page 5 of 14 input frequency ra nge and selection the cy25568 input frequency range is 4 to 32 mhz. this range is divided into 3 s egments and controlled by 3-level frsel pin as given in ta b l e 1 . output clocks the cy25568 provides 4 separate output clocks, refout, ssclk1, ssclk2 and ssclk3, for use in a wide variety of applications.each clock output is described in detail. refout refout is a 3.3 volt cmos level non-modul ated copy of the clock at xin/clkin. ssclk1, 2 and 3 ssclk1, ssclk2 and ssclk3 are spread spectrum clock outputs us ed for the purpose of reducing emi in digital systems. each clock can drive separate nets with a capacitive load of up to 20 pf. the frequency function of these clock outputs are selected by using 3-level d0 and d1 digital inputs and are given in ta b l e 2 . ref is the same non-modulated frequency as the input clock. 1x, 2x, or 4x are modulated and multiplied (in the case of 2x and 4x) frequency of the input clock. ccj3 cycle-to-cycle jitter - 100 150 ps f in=32 mhz (refer to figure 4a) table 1. input frequency selection frsel input frequency range 0 4.0 to 8.0 mhz 1 8.0 to 16.0 mhz m 16.0 to 32.0 mhz table 2. output clocks function selection d0 d1 refout ssclk1 ssclk2 ssclk3 0 0 ref ref 1x 1x 0m ref 1x 2x 2x 0 1 ref ref 2x 2x m 0 ref ref 1x 2x m m ref ref ref ref m 1 ref ref 2x 4x 1 0 ref ref 4x 4x 1m ref 1x 2x 4x 11 ref 1x 2x 4x timing electrical characteristics test conditions: v dd =3.3 v, t=25 c, cl=15pf. rise/fall time at 0.4 and 2.4 v, duty cycle at 1.5 v
cy25568 document number: 38-07111 rev. *d page 6 of 14 spread % selection the cy25568 provides center-spread, down-spread and no-spre ad functions. these functions and the amount of spread% are selected by using 3-level s0 and s1 digital inputs and are given in table 3 . 3-level digital inputs figure 2. 3-level logic s0, s1, d0, d1, and frsel digital inputs of the cy25568 are designed to sense 3 different logic levels designated as high - 1, low- 0 and middle- m. with this 3-level digital input logic, t he cy25568 is able to detect 9 different logic states in the case of (s0, s1) and (d0, d1) logic pairs and 3 different logic states in the case of frsel. s0, s1, d0, d1, and frsel pins include an on chip 20k (10k /10k) resistor divider. no external application resistors are needed to implement the 3-level logic levels as shown in the following: logic state 0 = 3-level logic pin connected to gnd. logic state m = 3-level logic pin left floating (no connection). logic state 1 = 3-level logic pin connected to vdd. figure 2 illustrates how to implement 3-level logic. table 3. spread% selection xin (mhz) frsel s1=0 s0=0 s1=0 s0=m s1=0 s0=1 s1=m s0=0 s1=1 s0=1 s1=1 s0=0 s1=m s0=1 s1=1 s0=m s1=m s0=m center (%) center (%) center (%) center (%) down (%) down (%) down (%) down (%) no spread 4-5 0 +/?1.4 +/?1.2 +/?0.6 +/?0.5 ?3.0 ?2.2 ?1.9 ?0.7 0 5-6 0 +/?1.3 +/?1.1 +/?0.5 +/?0.4 ?2.7 ?1.9 ?.7 ?0.6 0 6-7 0 +/?1.2 +/?0.9 +/?0.5 +/?0.4 ?2.5 ?1.8 ?1.5 ?0.6 0 7-8 0 +/?1.1 +/?0.9 +/?0.4 +/?0.3 ?2.3 ?1.7 ?1.4 ?0.5 0 8-10 1 +/?1.4 +/?1.2 +/?0.6 + /?0.5 ?3.0 ?2.2 ?1.9 ?0.7 0 10-12 1 +/?1.3 +/?1.1 +/?0.5 +/?0.4 ?2.7 ?1.9 ?1.7 ?0.6 0 12-14 1 +/?1.2 +/?0.9 +/?0.5 +/?0.4 ?2.5 ?1.8 ?1.5 ?0.6 0 14-16 1 +/?1.1 +/?0.9 +/?0.4 +/?0.3 ?2.3 ?1.7 ?1.4 ?0.5 0 16-20 m +/?1.4 +/?1.2 +/?0.6 +/?0.5 ?3.0 ?2.2 ?1.9 ?0.7 0 20-24 m +/?1.3 +/?1.1 +/?0.5 +/?0.4 ?2.7 ?1.9 ?1.7 ?0.6 0 24-28 m +/?1.2 +/?0.9 +/?0.5 +/?0.4 ?2.5 ?1.8 ?1.5 ?0.6 0 28-32 m +/?1.1 +/?0.9 +/?0.4 +/?0.3 ?2.3 ?1.7 ?1.4 ?0.5 0 logic low (0) logic middle (m) logic high (h) d0, d1, s0, s1 and frsel to vdd d0, d1, s0, s1 and frsel unconnected do, d1, s0, s1 and frsel to gnd vdd gnd
cy25568 document number: 38-07111 rev. *d page 7 of 14 power-down (pd#) cy25568 includes a power-down (pd#, pin 10) function. this input uses standard 2-level cmos logic and is internally pulled up t o vdd (high). connect this pin to gn d if power is to be turned off. modulation rate spread spectrum clock generators use frequency modulation (fm) to distribute energy over a specific band of frequencies. the maximum frequency of the clock (fmax) and minimum frequency of the clock (fmin) determine this band of frequencies. the time required to transition from fmin to fmax and back to fmin is the period of the modulation rate , tmod. the modulation rate of ss cg clocks are generally referred to in terms of frequency or fmod = 1/tmod. the input clock frequency, fin, and the intern al divider determine the modulation rate. in the case of cy25568, the (spread spectrum) modulati on rate is given by the fo llowing formula: fmod = fin/dr where; fmod is the modulation rate, fin is the inpu t frequency and dr is the divider ratio as given in table 4 . notice that input frequency range is set by frsel. table 4. modulation rate frsel input frequency range (mhz) divider ratio (dr) 0 4 to 8 128 1 8 to 16 256 m 16 to 32 512
cy25568 document number: 38-07111 rev. *d page 8 of 14 characteristic curves the following curves demonstrate the characteristic behavior of the cy25568 when tested over a number of environmental and application specific parameters. these are typical performance cu rves and are not meant to replace any parameter specified in t ables ?dc electrical characteristics? on page 4 and ?timing electrical characteristics? on page 4. figure 3. jitter vs. input frequency (no load) figure 4. bandwidth% vs. temperature figure 5. idd vs. frequency (frsel = 0, 1, m) figure 6. bandwidth% vs. vdd 0 100 200 300 400 500 600 4 8 12 16 20 24 28 32 input fr equency ( m hz ) ccj (p s ) 1.75 2 2.25 2. 5 2.75 -40 -25 -10 5 20 35 50 65 80 95 110 125 temp ( c) bw % 6.0 mhz 32.0 mhz 10 12 14 16 18 20 22 24 26 28 30 44.555.566.577.58 fre qu ency (m hz ) n o load, no rm aliz e d to frsel = 0, ( 4 - 8 mhz ) . idd (ma) frsel = 0 4 - 8 mhz frs el = 1 8 - 16 m hz frse l = m 16 - 32 mhz 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 2. 8 2.9 3 3. 1 3.2 3.3 3.4 3. 5 3.6 3. 7 vdd (volts) bw (%) 4.0 mhz 8.0 mhz
cy25568 document number: 38-07111 rev. *d page 9 of 14 sscg profiles the cy25568 uses a non-linear frequency profile as shown in figure 7 . the use of cypress proprietary ?optimized? frequency profile maintains flat energy distribution over th e fundamental and higher order harmonics. this results in additional emi reduction in electronic systems. figure 7. spread spectrum profiles (frequency versus time) ? xin = 6.0 mhz ssclk1 = 6.0 mhz s 1 , s0 = 0 d1 , d 0 = 1 x in = 24.0 mhz ssclk1 = 24.0 mhz s1 , s0 = 0 d1 , d0 = 1 xin = 12.0 mhz ssclk1 = 48.0 mhz s 1 , s0 = 0 d1 , d 0 = 1 x in = 24.0 mhz ssclk1 = 96.0 mhz s 1 , s0 = 0 d1 , d 0 = 1
cy25568 document number: 38-07111 rev. *d page 10 of 14 application schematic figure 8. application schematic ordering code definitions ordering information part no. package operating temperature range pb-free cy25568sxc 16 pin soic 0 to 70 ? c CY25568SXCT 16 pin soic ? tape and reel 0 to 70 ? c t = tape and reel; blank = tube temperature range: c = commercial pb-free package: s = 16-pin soic base part number company id: cy = cypress 25568 cy s x t c
cy25568 document number: 38-07111 rev. *d page 11 of 14 package diagram figure 9. 16-pin (150-mil) soic 51-85068 *c
cy25568 document number: 38-07111 rev. *d page 12 of 14 acronyms document conventions units of measure acronym description dvd digital versatile/video disc emi electromagnetic interference i/o input/output lan local area network lcd liquid crystal display pll phase-locked loop soic small-outline integrated circuit ssc spread spectrum clock sscg spread spectrum clock generator vcd video compact disc wan wide area network symbol unit of measure % percent c degree celsius db decibel ma milliamperes mhz megahertz mm millimeter ms milliseconds mw milliwatts ns nanoseconds pf picofarad ps picoseconds vvolts ? ohms wwatts
cy25568 document number: 38-07111 rev. *d page 13 of 14 document history page document title: cy25568 spread spectrum clock generator document number: 38-07111 rev. ecn orig. of change submission date description of change ** 107515 ndp 06/14/01 convert from imi to cypress *a 108182 ndp 07/03/01 delete ?junction temp? in absolute maximum ratings (page 4) *b 122682 rbi 12/21/02 added power-up requirements to absolute maximum ratings information. *c 2658020 kvm/pyrs 02/16/09 updated ordering info rmation table with pb-free part numbers. deleted the table ?16 pin soic outline dimensions (150 mil)? updated template *d 3319217 bash 07/08/18 update to latest template added ordering code definitions updated package diagram added acronyms added units of measure added contents
document number: 38-07111 rev. *d revised july 18, 2011 page 14 of 14 cy25568 ? cypress semiconductor corporation, 2001-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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